These are explained in several documents. There is ONE actual external SDRAM available on this board. In Qsys and uses the pool of available M10K blocks.Įasy to use, bus attached memory, which can be accessed from FPGA and HPS.
Qsys-attached startic RAM (M10K blocks)Įasy to use, bus attached memory, which can be accessed from FPGA and HPS. Up to 128,000 bits of memory, but this uses general logic elements very quickly. You see the written data at the output port without the need for a read clock rising edge. For example, when you write a data at the write clock rising edge and after the write operation is complete, Up to about 480 blocks, each holding 16, 18 or 20 words There are optional input pipeline registers on data, address, write-enable, so a M10K block read takes 3-cycles if the input registers are enabled, but can be pipelined. There is a data-out pipeline register, which delayss the read by one cycle, for a total of two cycles. If you instantiate bigger memories in Verilog, blocks will be automatically concantenated to build the bigger memory. I will not talk about the HPS side here, only the FPGA side. 
The memory systems of Altera Cyclone5 FPGAs have various features and limitations.
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